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RM0008
8.2.6
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Port bit reset register (GPIOx_BRR) (x=A..G)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
BR15
w
14
BR14
w
13
BR13
w
12
BR12
w
11
BR11
w
10
BR10
w
9
BR9
w
8
BR8
w
7
BR7
w
6
BR6
w
5
BR5
w
4
BR4
w
3
BR3
w
2
BR2
w
1
BR1
w
0
BR0
w
Bits 31:16
Reserved
Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit
8.2.7
Port configuration lock register (GPIOx_LCKR) (x=A..G)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit it is no longer possible to modify the value of
the port bit until the next reset.
Each lock bit freezes the corresponding 4 bits of the control register (CRL, CRH).
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LCKK
Reserved
rw
15
LCK15
rw
14
LCK14
rw
13
LCK13
rw
12
LCK12
rw
11
LCK11
rw
10
LCK10
rw
9
LCK9
rw
8
LCK8
rw
7
LCK7
rw
6
LCK6
rw
5
LCK5
rw
4
LCK4
rw
3
LCK3
rw
2
LCK2
rw
1
LCK1
rw
0
LCK0
rw
Bits 31:17
Reserved
Doc ID 13902 Rev 9
151/995
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